1. Field of the Invention
The present invention relates to a semiconductor package and a met hod for manufacturing the same. More particularly, the present invention relates to a bumped chip carrier package using a lead frame and a method for manufacturing the same.
2. Description of the Related Art
In an effort to reduce the size and weight of multi-function electronic devices while simultaneously increasing speed and performance, high-density integrated circuits (ICs) are being mounted in high-density packages. One such high-density package is a chip scale package (CSP), wherein ICs are mounted directly on a substrate. Although such CSPs have been manufactured in sizes as small as a single IC, a CSP may provide for the mounting of multiple ICs on a common substrate or carrier, such as a printed circuit board (PCB), a tape circuit board, or a lead frame. One such conventional CSP is a bumped chip carrier (BCC) package, which uses a lead frame as shown in FIG. 1 through 3, wherein FIG. 2 illustrates a cross-sectional view taken along line 2—2 in FIG. 1.
Referring to the two views of the BCC package shown in FIGS. 1 and 2, a semiconductor chip 20 is attached to a chip mounting area 12 of a lead frame 10, and a plurality of contact grooves 14 are formed around the periphery of the chip mounting area 12. Each one of a plurality of bonding pads 24 on semiconductor chip 20 are electrically connected to an associated contact groove 14 by a bonding wire 30. The semiconductor chip 20, the plurality of bonding wires 30, and the plurality of contact grooves 14 on lead frame 10 are then encapsulated with a molding resin to form a resin mold 40.
Each contact groove 14 typically includes a depression having an overlaying plating layer 16, which is formed by successive deposition and/or etching of metal layers using metals, such as stannum (Sn), palladium (Pd), and aurum (Au). Since it is difficult to attach a bonding wire 30 directly to the concave plating layer 16, a conventional procedure for connecting the bonding wire 30 to the plating layer 16 is typically a two-step process.
In a first step, a first plurality of ball solder bumps 32 are formed on each one of the contact locations on plating layer 16 using a ball bonding technique. A second plurality of ball solder bumps are then formed on each one of the bonding pads 24 of semiconductor chip 20. A stitch bonding operation is then performed to connect each end of the bonding wires 30 to the associated ball solder bumps.
An alternate variation on this conventional CSP might feature the elimination of lead frame 10 under the resin mold 40 by using a selective etching, such as that shown by the conventional bumped chip carrier package 50 of FIG. 3. In bumped chip carrier package 50, an external contact terminal 18 has a structure in which plating layer 16 is filled with a molding resin.
Because the height of the external contact terminals 18 in the bumped chip carrier package 50 may be adjustably controlled during the manufacturing process of the lead frame, the bumped chip carrier package 50 has a significant advantage over conventional semiconductor chip mounting techniques using conventional solder balls as an external contact terminal.
Disadvantageously, however, since a conventional external contact terminal structure features a plating layer 16 being filled with a molding resin, plating layer 16 may exhibit cracking due to a difference in thermal expansion coefficients between the plating layer 16 and the molding resin during conventional manufacturing tests of bumped chip carrier package 50, for example, during a temperature cycling (T/C) test. Another significant disadvantage of conventional CSPs is that the aforementioned two-step ball bonding operation is typically required in the wire bonding process.